1. Field of the Invention
The present invention relates to a receiving apparatus, a receiving method and program, and a receiving system and, more particularly, to a receiving apparatus, a receiving method and program, and a receiving system that are configured to reduce the power consumption in bad conditions while normally decoding LDPC (Low Density Parity Check) codes in good conditions.
2. Description of the Related Art
Having strong error correction capabilities, LDPC codes are employed the DVB-S2 (Digital Video Broadcasting—Satellite—Second Generation) standard and the DVB-T2 (Digital Video Broadcasting-Terrestrial 2) standard for use in digital television systems based on these broadcasting standards for example.
An LDPC code is repetitively decoded to provide high error correction capabilities. However, the repetition of decoding results in increasing the power consumption of digital television systems. Besides, the data amount per code word of LLR (Log-Likelihood Ratio) that is entered in a reception apparatus as an LDPC code depends on a symbol rate and so on. Consequently, the number of repetitions of decoding that can be executed in a given period of time varies. Further, if there is a variation in the data amount per code word of LDPC code, a deviation occurs in the timing of decoding, thereby causing a large variation in power consumption.
Now, referring to FIG. 1, there is shown a block diagram illustrating a receiving apparatus configured to receive LDPC codes.
A receiving apparatus 10 shown in FIG. 1 is composed of an LDPC decoding block 11 and a repetition count control block 12.
The LDPC decode block 11 receives a log-likelihood ratio as an LDPC code for each frame entered from the outside in response to a decode enable signal for enabling the reception of LLR supplied from the repetition count control block 12. The LDPC decode block 11 executes LDPC decoding by use of the received log-likelihood ratio. The LDPC decode block 11 determines on the basis of a decoding result whether the LDPC decoding has been successful or not. Then, depending on the determination result, the LDPC decode block 11 supplies a decode successful flag indicative of successful LDPC decoding or a decode unsuccessful flag indicative of unsuccessful LDPC decoding to the repetition count control block 12. In addition, as specified by the repetition count control block 12, the LDPC decode block 11 outputs a decode result.
A frame start signal indicative of a frame start timing is entered in the repetition count control block 12. In response to the frame start signal, the repetition count control block 12 enters a decode enable signal into the LDPC decode block 11. It should be noted that, if the level of a decode enable signal is H (High) level, the reception of log-likelihood ratio is enabled; if the level of a decode enable signal is L (Low) level, the reception of log-likelihood ratio is disabled.
If a decode successful flag is supplied from the LDPC decode block 11, the repetition count control block 12 instructs the LDPC decode block 11 to output the decoding result. On the other hand, if a decode unsuccessful signal is supplied from the LDPC decode block 11, the repetition count control block 12 instructs the LDPC decode block 11 to executing decoding again before the frame start signal of a next frame is received and, when the frame start signal of a next frame is received, instructs the LDPC decode block 11 to output a decoding result.
Referring to FIG. 2, there is shown a flowchart indicative of the decode processing that is executed by the receiving apparatus 10. This processing starts when a decode enable signal of H level is entered from the repetition count control block 12 into the LDPC decode block 11 in response to the frame start signal of a start frame.
In step S11, the LDPC decode block 11 receives a log-likelihood ratio for each frame from the outside. Upon reception of the log-likelihood ratio, the decode enable signal goes L level. In step S12, the LDPC decode block 11 executes LDPC decoding by use of the received log-likelihood ratio. In step S13, the LDPC decode block 11 determines on the basis of a decoding result whether the LDPC decoding has been successful or not.
If the LDPC decoding is found successful in step S13, then the LDPC decode block 11 supplies a decode successful flag to the repetition count control block 12. In response, the repetition count control block 12 instructs the LDPC decode block 11 to output a decoding result. Next, in step S14, the LDPC decode block 11 outputs a decoding result.
In step S15, the repetition count control block 12 determines whether a new frame start signal has been entered or not. If no new frame start signal is found entered in step S15, the repetition count control block 12 waits until a new frame start signal is entered.
On the other hand, if a new frame start signal is found entered in step S15, then the repetition count control block 12 enters a decode enable signal of H level into the LDPC decode block 11, returning the processing procedure to step S11. Consequently, the LDPC decoding for log-likelihood ratio of a frame next to the frame subject to the previous decoding.
If the LDPC decoding is found unsuccessful in step S13, the LDPC decode block 11 supplies a decode unsuccessful flag to the repetition count control block 12. Next, in step S16, the repetition count control block 12 determines whether a new frame start signal has been entered or not.
If no new frame start signal is found entered in step S16, then the repetition count control block 12 instructs the LDPC decode block 11 to execute decoding and returns the processing procedure to step S12. Then, the processing operations of steps S12, S13, and S16 are repeated until LDPC decoding is found successful or a new frame start signal is entered.
On the other hand, if a new frame start signal is found entered in step S16, then the repetition count control block 12 enters a decode enable signal of H level.
Next, in step S17, the LDPC decode block 11 outputs a decoding result in response to the instruction supplied by the repetition count control block 12. Thus, the receiving apparatus 10 is able to repeat the LDPC decoding until the LDPC decoding is successful in a period of time up to the input of a frame start signal of the frame next to the current frame subject to decoding. After the processing of step S17, the processing procedure returns to step S11 to execute the LDPC decoding for the log-likelihood ratio of the frame next to the frame subject to the previous decoding.
Referring to FIG. 3, there is shown a timing chart indicative of operation timings of the receiving apparatus 10 in a condition where the BER (Bit Error Rate) of a decoding result is relatively low. FIG. 4 shows a timing chart indicative of operation timings of the receiving apparatus 10 in a condition where the BER of a decoding result is relatively high.
As shown in FIG. 3, in the condition where the BER of a decoding result is relatively low, error correction converges with a relatively small repetitive decoding count, so that the power consumption is held down by stopping the LDPC decoding if the LDPC decoding is successful.
On the other hand, as shown in FIG. 4, in the condition where the BER of a decoding result is relatively high, the repetitive execution of decoding cannot sufficiently execute the error correction, so that the decoding is repeated until the input of a next frame start signal. This keeps the power consumption always at a high level.
So, techniques were proposed that, if the repetitive execution of decoding cannot achieve the sufficient error correction, the repetitive decoding is stopped by detecting the insufficient error correction, thereby holding down the power consumption (refer to JP-T-2008-544692 and Japanese Patent Laid-open No. 2007-81640).
Further, a technique was proposed that the repetitive decoding count is controlled on the basis of communication path conditions, such as signal-to-noise ratio (SNR), noise power, noise quantity, and so on (refer to Japanese Patent Laid-open No. 2009-38707).